Formation of low resistance via contacts in interconnect structures

ABSTRACT

A method of fabricating an interconnect structure including the steps of: forming a porous or dense low k dielectric layer on a substrate; forming single or dual damascene etched openings in the low k dielectric; placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and activating at a temperature about −200° C. to about 25° C. Also provided is an interconnect structure having a substrate, a conductive material disposed on the substrate, a porous or dense low k dielectric layer disposed on the conductive material, wherein the low k dielectric layer has a single or dual damascene etched openings that expose a surface of the conductive material, and metallic lines and vias etched onto the low k dielectric layer; wherein the exposed conductive material has been treated with a CCA and activated in the cold to remove oxide, oxygen and carbon containing residues from the surface of the conductive material.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to integrated circuits (ICs).More particularly, the present invention relates to interconnectstructures, including multilevel interconnect structures fabricated bydamascene methods in which the via contact resistance must be low. Thepresent invention describes various methods and tooling for makingimproved interconnect structures based on copper damascene wiring havinga reduced via contact resistance and stable resistance both during ICoperation and reliability stress of the IC device.

2. Description of the Prior Art

Generally, semiconductor devices include a plurality of circuits, whichform an integrated circuit fabricated on a silicon single crystalsubstrate. A complex network of signal paths will normally be routed toconnect the circuit elements distributed on the surface of thesubstrate. Efficient routing of these signals across the device requiresthe formation of multi-level or multi-layered interconnection schemes,such as, dual damascene wiring structures based on copper. Copper basedinterconnects are desirable due to their efficacy in providing highspeed signal transmission between large numbers of transistors on acomplex semiconductor chip.

Within the interconnection structure, metal vias run perpendicular tothe silicon substrate and metal lines run parallel to the siliconsubstrate. Further enhancement of the speed of signals and reduction ofinteraction of signals in adjacent copper lines (known as “cross-talk)is achieved in new IC product chips by surrounding the copper lines andvias in a low k or ultralow k dielectric.

Presently, interconnect structures formed on an integrated circuit chipincludes at least about 2 to 10 wiring levels fabricated at a minimumlithographic feature size designated about 1× (referred to as“thinwires”) and above these levels are about 2 to 4 wiring levelsfabricated at a larger size (referred to as “fatwires”). In one class ofprior art structures, the thinwires are formed in a low dielectricconstant (k) material having a dielectric constant between about 2 andabout 3.5.

However, fabrication problems are associated with these prior artstructures. For example, the via contact resistance is high in priorstructures due to contamination at the via to line interface.Contamination primarily includes oxygen and/or carbon and is in the formof copper oxide (Cu Oxide) or a carbon based residue (polymeric oramorphous carbon). The carbon residue commonly contains H or F and otherundesired elements may be present at the via to line interface.

Another problem associated with these prior art structures is pooradhesion at the via contact, which leads to increased via resistanceafter the structure is cycled in temperature or after long periods offield operation. The extreme case of increased via resistance is an openvia with no contact to the line below, a fatal IC failure mode. Pooradhesion is also due to the same contamination described above.

A further problem during interconnect fabrication is that the shapes anddimensions of the etched via and trench openings are correct after etch,but the shapes and dimensions are distorted, enlarged, degraded orroughened during via cleaning. This problem is most acute when lowmodulus ultralow k (ULK) dielectrics (k<about 2.7) are used and the viacleaning includes Ar+ bombardment. The Ar+ ions enlarge the viadimensions and erode the bottom of the trenches and even causeroughening of the trench bottom. Pores in the ULK dielectric make thisproblem severe.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide methods ofimproved fabrication of BEOL interconnect structures of the dual orsingle damascene type, with low via contact resistance.

It is also an object of the present invention to provide methods ofimproved fabrication of BEOL interconnect structures of the dual orsingle damascene type, in which all the vias on the IC are very stablein resistance (the via resistance does not change or goes down) afterthermal cycling of the structure.

It is a further object of the present invention to provide methods forimproved fabrication of BEOL interconnect structures of the dual orsingle damascene type in which all the vias on the IC have improvedadhesion.

It is a further object of the present invention to provide methods forimproved fabrication of BEOL interconnect structures of the dual orsingle damascene type in which the shapes of the etched via and trenchopenings are not distorted or changed during via cleaning.

It is a further object of the present invention to provide methods forimproved fabrication of BEOL interconnect structures of the dual orsingle damascene type in which the bottoms of the etched trench openingsare smooth after via cleaning and the other surfaces of the vias andlines remain smooth.

In keeping with these and other objects of the present invention,provided here are improved methods to clean the via contacts.

The above objects can be achieved by cleaning the via contact surfacesduring fabrication of an interconnect structure.

Accordingly, the present invention provides a general method of making aBEOL interconnect structure including a porous or dense low k dielectrichaving low via contact resistance. The method includes the steps of:

-   -   a) forming a porous or dense low k dielectric layer on a        substrate;    -   b) forming single or dual damascene etched openings in the low k        dielectric;    -   c) placing the substrate in a process chamber on a cold chuck at        a temperature about −200° C. to about 25° C.;    -   d) adding to the process chamber a condensable cleaning agent        (CCA) to condense a layer of CCA within the etched openings on        the substrate; and    -   e) performing an activation step while the wafer remains cold at        a temperature of about −200° C. to about 25° C.

The present invention further provides a method of making a BEOLinterconnect structure including a porous or dense low k dielectrichaving low via contact resistance. The method includes the steps of:

-   -   a) forming a porous or dense low k dielectric layer on a        substrate;    -   b) forming single or dual damascene etched openings in the low k        dielectric;    -   c) placing the substrate in a first process chamber on a cold        chuck at a temperature about −200° C. to about 25° C.;    -   d) adding to the first process chamber a condensable cleaning        agent (CCA) to condense a layer of CCA within the etched        openings on the substrate;    -   e) moving the substrate to a second process chamber on a cluster        tool; and    -   f) performing an activation step in the second process chamber.

The present invention still further provides a BEOL interconnectstructure including a porous or dense low k dielectric having low viacontact resistance prepared by the above methods of the presentinvention.

The via contacts prepared by the methods of the present invention arevery stable during thermal cycles and during operation of thesemiconductor device. Further, the via contacts prepared by the methodsdescribed herein have a lower resistance than the vias described in theprior art. In addition, in the present invention, the vias aresurrounded by a liner (for example, see element 6 in FIG. 1) and theadhesion of the liner is stronger than it is in the vias described inthe prior art. As a result, the interconnect structures of the presentinvention are more reliable and more stable than the interconnectstructures of the prior art, because stronger liner adhesion leads tomore reliable and stable interconnect structures.

These and other advantages of the present invention would be betterunderstood from the detailed description of the invention and thepreferred embodiments with reference to the drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a completed interconnectlevel having a first layer having a set of metallic lines and viastherein and a diffusion barrier layer thereon.

FIG. 2 is a schematic cross-sectional view of the etched via and lineopenings before any metallization of the openings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a non-destructive pre-clean processmethods for liner/barrier deposition on low-k dielectrics.

In general, an integrated circuit will have interconnect levels, eachlevel including metallic lines and vias that are of a dual damascene(via plus next level conductor) wiring interconnect structure for use onthe IC chip. The metallic lines and vias are composed of the same ordifferent conductive material. Suitable materials for use hereininclude, but are not limited to, W, Cu, Al, Ag, Au and alloys thereofand the like. A particularly preferred material is Cu.

The condensable cleaning agent (CCA) can be a reducing agent; metalbased reducing agent, metal hydride; mixed metal hydride such as, LiAIH,molecular source of fluorine or a source of hydrogen, or a source ofboth hydrogen and silicon.

Examples of the latter include, but are not limited to disilane;trisilane; tetrasilane and other condensable silanes.

Molecular sources of fluorine include metal fluorides, such as, AlF3,TiF4, WF6, TaF6 and include inorganic fluorine compounds, such as, SF6,XeF2 and a mixture thereof; organic fluorine sources such ashexafluoroproplyeneoxide, hexafluorobenzene, and include fluorinatedhigher silanes. Mixtures of the above compounds may be especiallyeffective as the CCA.

Generally, the hydrides and hydrogen sources are effective to removeoxide and oxygen containing residues, while fluorine sources are used toremove carbon containing residues. Preferably, the activation step canbe carried out by bombarding with He+ ions, H2+ ions and/or H+/H2+mixtures. Alternatively, the activation step can be carried out byirradiating with electron beam or irradiating with an ultraviolet (UV)radiation.

The activation step can be carried out by lifting the substrate off thecold chuck with lift pins and thereafter heating the substrate withheating lamps.

Preferably, the lifted substrate is heated to a temperature about 350°C. to about 400° C., more preferably, the lifted substrate is heated toa temperature about 200° C. to about 450° C.

Referring to FIG. 1, an example of dual damascene level is described inwhich a substrate 10 and an etch stop/barrier layer 2 are shown. On theetch stop/barrier is deposited the ILD 3 and an optional hardmask 4 isatop the ILD. It should be noted that the hardmask can be composed of asingle or multiple layers to form a composite hardmask film. A Cuconductor 5 is formed within the ILD, separated from the ILD by theliner/Cu diffusion barrier 6.

A second etch stop/barrier layer 7 forms the “cap” on the Cu conductor.Each of the metallic lines and vias 5 can optionally include a linermaterial 6, which lines the metallic lines and vias.

Suitable materials that can be used as liners include, but are notlimited to, TiN, TaN, Ta, WN, W, TaSiN, TiSiN, WCN, Ru and the like andmixtures thereof. The liner can be a single layer or it can includemultiple layers.

Techniques and parameters for forming the metallic lines and vias areknown in the art. Briefly, openings for defining lines and vias areformed utilizing conventional lithography (including applying aphotoresist to a surface of the low-k organic dielectric layer) andetching. The etching step includes a conventional dry etching, such as,reactive ion etching, ion beam etching or plasma etching. Thephotoresist is then stripped from the layer utilizing conventionalstripping processes.

Next, a conductive material is deposited on the liner, if one is used,or on the exposed surfaces of the openings employing conventionaldeposition processes, such as, CVD, plasma-assisted CVD, sputtering,plating, evaporation or chemical solution deposition. The conductivemetal filled structure is then subjected to a conventional planarizationprocess in which any residual conductive metal and/or liner outside theopening is substantially removed. For example, CMP may be used and afterCMP the top horizontal portions of the metallic lines are approximatelycoplanar with the top surface of the first layer.

A diffusion barrier layer 7 can then be deposited as a continuous layeron the top surface thereof to complete the interconnect level. Diffusionbarrier layer 7 is composed of any insulating material that is capableof preventing one of the above mentioned conductive metals fromdiffusing into the first layers formed above this interconnect level.

The present invention, which is directed to cleaning of the via openingsincluding the via contact to Cu line, is described in reference to FIG.2.

Referring to FIG. 2, a via opening 50 and a line opening 70 etched in adielectric layer 30 are shown. It should be noted that dielectric layer30 may be homogeneous, or it may be composed of multiple layers. Ifmultiple layers are presented, the interface between the two layers doesnot have to be concurrent with the interface between the line opening 70and the via opening 50.

The dielectric may have k from 3.5 to 2, as described below. Below thedielectric 30 is a barrier/cap/etch stop layer 20 disposed atop a copperline below 100. The dielectric layer 30 may include an optional hardmasklayer 40 which may be composed of a single or multiple layers to form acomposite hardmask film.

All of the above components are disposed on a substrate 110.

After formation (by dry etching) of the openings 50 and 70, attention isdrawn to the bottom of the via opening, where the barrier/cap/etch stoplayer 20 has an etched opening 90. Opening 90 is known as the viabottom, where Cu 101 is exposed. The Cu surface may contain a Cu Oxidelayer 120 due to Cu oxidation by the air, aqueous cleaning solution,partially oxygenated solvent cleaning solution, and other sources ofoxygen such as the reactive feed gases used to form opening 90 inbarrier/cap/etch stop layer 20. The Cu Oxide layer 120 may containcarbon and other elements. Also present within the via opening may be avariable thickness of carbon residue 140, which may contain H, F andother elements, may be polymeric or may be an amorphous carbon typematerial.

The carbon residue 140 is commonly present at the via bottom althoughFIG. 2 shows the residue on the sidewalls.

Commonly in the prior art, the residue 140 is removed by H atoms andother active species using a reducing H2 plasma or an oxidizing plasma,in a first cleaning step. Other common chemistries include one or moreof the following gases: H2, O2, N2 and NH3.

The Ar+ ions employed in the prior art typically have kinetic energiesfrom about 100 eV to about 1000 eV are used to remove the Cu Oxide 120in a second cleaning step. When Ar+ ions are used, the ions cause damageto the exposed trench bottom 150 and to hardmask 40, where thedielectric is directly exposed to Ar+ bombardment.

During removal of the Cu Oxide layer, Cu atoms are sputtered from thevia bottom onto the via sidewalls 160 and onto the trench floor, whereCu on the trench floor is shown as 155.

The substrate 110 may be a semiconductor wafer or chip that can becomposed of any silicon-containing semiconductor material, such as, forexample, Si, SiGe, Si/SiGe, Si/SiO₂/Si and the like. The substrate maybe doped with dopants either n- or p-type depending on the desireddevice to be fabricated. The substrate may contain various isolationand/or device regions either formed in the substrate or on a surfacethereof. The substrate may also contain metallic pads on the surfacethereof. In addition to silicon-containing semiconductor materials, thesubstrate may be a circuit that includes CMOS devices therein.

Suitable dielectrics for layer 30 are porous or dense inorganicmaterials including, but not limited to, silicon-containing materialssuch as compositions formed from one or more of Si, C, O, F and H, e.g.,FSG, C doped oxide, F doped oxide, alloys of Si, C, O and H and thelike. Specific examples of PE CVD materials of the composition Si, C, O,and H include, but are not limited to, Black Diamond from AppliedMaterials, Coral from Novellus Systems and Aurora from ASM., all have kapproximately 3.0, and include the range 2.8 to 3.2. Also, SiCOHdielectrics containing porosity and having k from 2.7 down to 1.8 may bepreferably used within this invention, including BDII and BDIII fromApplied Materials, Aurora ULK and ELK from ASM, and other porous SiCOHfilms. A variety of spin applied films having the composition Si, C, O,H, such as, methylsilsesquioxanes, siloxanes and 5109, 5117, 5525, 5530from Japan Synthetic Rubber (JSR), and Dendriglass may also be used. Thematerials known as Orion and other materials from Trikon may also beused.

Techniques and parameters for forming first dielectric layer 30 onsubstrate 110 (e.g., PE CVD or spin coating) are within the purview ofone skilled in the art. As is known in the art, PECVD from a cyclicprecursor and a second hydrocarbon precursor is one preferred method tomake SiCOH dielectrics with k between 2 and 3, as disclosed in U.S. Pat.Nos. 6,312,793; 6,441,491; and 6,479,110 B2, the contents of which areincorporated herein by reference.

Alternatively, the dielectric layer 30 may be a low-k organic materialssuch as the commercially available organic thermoset materials availablefrom Dow Chemical Co. sold under the tradename SILK™ or polyaryleneethers and the like. Additionally, dielectric layer 30 may beporous-SiLK™ from Dow Chemical Company.

Each of the present methods for via cleaning begins by placing thesubstrate containing elements 100-160 (see above) on a cooled waferchuck at a temperature about −200 to about 25° C. and then a condensablecleaning agent (CCA) is added to the process chamber for a period fromabout 1 second to about 100 seconds, a time sufficient to condense from0.1 to 100 monolayers of CCA.

As mentioned above, the condensable cleaning agent (CCA) is selectedfrom reducing agents, molecular sources of fluorine, hydrogen sourcesand a source of both hydrogen and silicon.

Examples of the reducing agents include metal based reducing agents,such as, metal hydride; mixed metal hydrides, such as, LiAlH.

Examples of the source of both hydrogen and silicon include, but are notlimited to, disilane; trisilane; tetrasilane and other condensablesilanes.

Molecular sources of fluorine include metal fluorides, such as, AlF3,TiF4, WF6, TaF6 and include inorganic fluorine compounds, such as, SF6,XeF2 and a mixture thereof; organic fluorine sources such ashexafluoroproplyeneoxide, hexafluorobenzene, and include fluorinatedhigher silanes.

Mixtures of the above compounds may be especially effective as the CCA.

The preferred CCA's include disilane, higher silanes such as trisilane,metal hydride compounds, metal fluoride compounds such as AlF3, TiF4,WF6, TaF6, inorganic fluorine compounds, such as, SF6 or XeF2, mixedfluorinated higher silanes, mixed metal hydrides and fluorides and thelike. Metal based reducing agents such as LiAlH, is also preferred.

In the methods of the present invention, the CCA is condensed on thecold wafer in the coating step, forming a thin layer in the via bottom(and roughly uniformly all across the wafer). Next, the CCA is activatedin the activation step, the carbon-based contamination is converted tovolatile organic compounds and the Cu Oxide is removed from the Cusurfaces.

In one embodiment, the activation step is performed by He+ ion or He+and H+/H2+ bombardment while the wafer remains cold and 1 processchamber is used. In the bombardment step, He, and optionally H2, areflowed into the process chamber at flow rates from about 1 sccm to about10000 sccm with a preferable flow rate range of about 100 to about 500sccm for each gas species.

In another embodiment, the activation step is performed by electron beamirradiation or UV irradiation while the wafer is cold and a singleprocess chamber is used. In the electron beam treatment, an electronenergy from about 0.5 eV to about 100 keV, a dose of about 10 to about1,000 micro Curies/cm² and a time of about 1 second to about 10,000seconds are employed. A typical condition for this treatment is anelectron energy from about 1 to about 10 keV, a dose of about 50 toabout 500 micro Curies/cm².

In still another embodiment, the activation step is performed by heatingthe wafer and a single process chamber is used. Specifically, the waferis lifted off the cold chuck using lift pins and then heating lamps areused to heat the lifted wafer to a temperature of about 350° C. to about400° C. and preferably from about 200° C. to about 450° C.

In yet another embodiment, the activation step is performed in aseparate process module on a cluster tool. First the substratecontaining elements 100 to 160 is placed on a cooled wafer chuck at atemperature of −200° C. to about 25° C. in the process chamber describedin the first embodiment and then, a condensable cleaning agent (CCA) isadded to the process chamber for a period sufficient to condense (fromabout 1 to about 100 seconds), which is a time sufficient to condensefrom about 0.1 to about 100 monolayers of CCA.

Thereafter, the substrate is moved to a second process chamber whereinthe substrate is irradiated with He+ ion or He+ and H+/H2+ ions, withelectron beam radiation, with UV radiation, with thermal energy, or withanother energy source.

In the second chamber, the wafer may not be lifted off the chuck. Thechuck may be heated, for example, resistively, with a heating fluid, orwith heating lamps, to the desired temperature.

In another embodiment, the activation step is performed using a noblegas plasma and at least 1 grid is placed between the plasma and thesubstrate. The grid is biased positive in order to repel positive ions,so that the substrate containing the condensed layer of CCA is activatedwith VUV light and electrons from the plasma. Optionally, a second gridis placed and biased negative to repel the electrons, so that only VUVlight activates the CCA.

While we have shown and described several embodiments in accordance withour invention, it is to be clearly understood that same are susceptibleto numerous changes that would be apparent to one skilled in the art.Therefore, we do not wish to be limited to only what is shown ordescribed but contemplate all changes and modifications that are withinthe scope of the appended claims.

1-40. (canceled)
 41. An interconnect structure comprising: a substrate;a conductive material disposed on said substrate; a porous or dense lowk dielectric layer disposed on said conductive material, wherein saidlow k dielectric layer has a single or dual damascene etched openingsthat expose a surface of said conductive material; and metallic linesand vias etched onto said low k dielectric layer; wherein said exposedsurface of said conductive material in said etched openings has beentreated with a condensable cleaning agent (CAA) and activated at atemperature about −200° C. to about 25° C. to remove oxide, oxygen andcarbon containing residues from said surface of said conductivematerial.
 42. The interconnect structure of claim 41, further comprisinga liner material lining said metallic lines and vias.
 43. Theinterconnect structure of claim 42, wherein said liner material isselected from the group consisting of: TiN, TaN, Ta, WN, W, TaSiN,TiSiN, WCN, Ru and a mixture thereof.
 44. The interconnect structure ofclaim 41, wherein said porous or dense low k dielectric is selected fromthe group consisting of: silicon-containing material formed from one ormore of Si, C, O, F and H, PE CVD materials having a composition Si, C,O, and H, a fluorosilicate glass (FSG), C doped oxide, F doped oxide andalloys of Si, C, O and H.
 45. The interconnect structure of claim 41,wherein said interconnect structure is placed in a first process chamberon a cold chuck to condense a layer of condensable cleaning agent withinsaid etched openings on said substrate and thereafter activated in asecond process chamber on a cluster tool.
 46. The interconnect structureof claim 41, wherein said metallic lines and vias are filled with Cu.47. The interconnect structure of claim 41, wherein said conductivematerial disposed on said substrate is selected from the groupconsisting of: W, Cu, Al, Ag, Au and alloys thereof.
 48. Theinterconnect structure of claim 47, wherein said conductive material isCu.